A Non-binary C-R Hybrid DAC for 12 b 100 MS/s CMOS SAR ADCs with Fast Residue Settling

Abstract

This work proposes two versions of a 12 b 100 MS/s successive-approximation register (SAR) ADC based on a non-binary C-R hybrid DAC. The proposed DAC applies a non-binary weighted capacitor array to the 7 MSBs to meet the settling requirement of the DAC output and determines the remaining 5 LSBs using the reference voltages generated from a simple resistor string to reduce the DAC area significantly. The Version 1 ADC in a 28 ㎚ CMOS adopts a synchronous SAR logic and a comparator with a tail capacitor and a reset switch to minimize power consumption. The Version 2 ADC in a 0.18 ㎛ CMOS employs an asynchronous SAR logic with simple meta-stability correction logic to achieve high-speed operation. The Version 1 ADC which has an active die area of 0.042 ㎟ shows a maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 62.3 and 77.3 ㏈, respectively, consuming 1.3 ㎽ with a 1.0 V supply voltage. The Version 2 ADC is based on a similar analog circuit topology, showing a maximum SNDR and SFDR of 60.1 and 73.5 ㏈, respectively, with an active die area of 0.30 ㎟, operating at a 1.8 V supply voltage.