Abstract
Based on N-well Chartered 0.35-um CMOS technology, we designed an integrator for a low-power and high-precision sigma-delta modulator, which has a structure of third-order CIFF, one bit quantization. Amplifier designed in this paper use the PMOS folded cascade differential structure. All switches of the switch capacitance integrator are CMOS switch. The structure-improved integrator can be used to preliminarily filter the noise power of the input signal, and reduce the noise into the modulator, combined with bottom plate sampling technology and the right timing sequence. Input sinusoidal signal has frequency of 65.625Hz and amplitude of 0.6V. It’s simulated in cadence spectre with sampling frequency of 76.8kHz and power supply voltage of 3.3V. FFT analysis of the integrator output shows that the noise floor is-94.3dB, which meets the performance requirements of the system.
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