A Noise Immune Double Suspended Gate MOSFET for Ultra Low-Power Applications

Abstract

The purpose of this paper is to develop the design and analytical modelling of a noise immune double suspended gate MOSFET (DSG-MOSFET) for ultra-low power applications. Also, important performance parameters of the proposed structure such as pull-in and pull-out voltages have been thoroughly investigated with respect to the valuable structural parameters. The design methodology used is EKV based analytical approach to calculate the pull-in and pull-out voltages with ingeniously developed boundary conditions which helps achieving reasonably accurate result. Also, the I-V characteristics has been modelled to justify accuracy. The experimental result shows that the pull-in and pull-out voltages are in millivolts and microvolts range and hence it can be used in ultra-low power applications. As the ratio between the pull-out and the pull-in voltage is 10^(+3) range, justifies that the proposed structure is noise immune. The ID-VGS characteristic has hysteresis and this sharp transition in pull-in and pull-out voltage indicates that it can be used as an ideal switch with infinite sub-threshold slope. This paper presents a compact EKV based analytical modelling of pull-in and pull-out voltages for a DSG-MOFET which predict the device characteristics reasonably similar to simulated results. Also, for the first time the noise immunity for a DSGMOSFET has been analyzed.