Abstract
In this article, a new wave-pipelining methodology named wave component sampling method, is proposed. In this method, only the component of a wave, whose maximum and minimum delay difference exceeds the tolerable value, is sampled, and the other components continue to propagate through the circuit. Therefore, the total number of registers required for synchronisation decreases significantly. For demonstrating the effectiveness of the proposed method, it is applied to 8 × 8 bit carry save adder multiplier using 90 nm CMOS technology. Monte Carlo and corner simulation results show that 8 × 8 bit multiplier can operate at a speed of 3.70 GHz, using only 70 latches. Comparing with the mesochronous pipelining scheme, the number of the registers is decreased by 41% and the total power consumption of the chip is also decreased by 8.3% without any performance loss.
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