A new vertical double diffused MOSFET—The self-aligned terraced-gate MOSFET

Abstract

A new power MOSFET structure with a Self-aligned Terraced Gate (STGMOSFET) is demonstrated. The unique gate structure of the STGMOSFET reduces the parasitic gate capacitances, resulting in improved high-frequency performance. The STGMOSFET structure was used to design a 3.5 mm × 3.5 mm transistor. This chip had an on-resistance of 2.3 Ω and a 500-V source-drain breakdown voltage. It exhibited excellent high-frequency performance with a cut-off frequency of 100 MHz, and rise and fall times of 5 and 20 nS, respectively.