A new variable topology for evolutionary hardware design

Abstract

In this paper, a novel variable topology for evolutionary hardware design is proposed. The slicing structure and routing graph are integrated into the design of evolutionary hardware. With off-line gate-level samples, simulation results clearly demonstrate the validity of this new approach performed as superior as existing methods in the logic circuit optimization. Compare with the random circuit matrix method, our approach uses less code length for evolutionary hardware description. The method we proposed could be taken as an alternative way for possible evolutionary hardware applications in the future.