Abstract
A new transistor structure for high speed bipolar LSI, named PEE (Polycrystalline Electrode with Epitaxy) transistor, has been developed especially with respect to base and collector geometry. The basic features of the new structure are ; (1) polycrystalline silicon electrodes for a base and a collector and also polycrystalline silicon resistors, and (2) two-step oxide isolation which enables the bottom side isolation of an extrinsic base to the collector. The new structure can minimize parasitic capacitance, for instance, CTC can be reduced to about half of the conventional oxide isolated structure. This results in a high cutoff frequency of 6.0 GHz. Gate delay time and power-delay product measured with five-stage ECL ring oscillators ranged from 0.74 nsec, 2.8 pJ to 1.3 nsec, 1.8 pJ, and the performance was improved approximately 20% compared with the conventional devices.
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