A new three-level fault tolerance arithmetic and logic unit based on quantum dot cellular automata

Abstract

Quantum-dot cellular automata (QCA) as a technology in the nanoscale is used for designing the future circuits. It has high density, speed, and low power dissipation. Besides, arithmetic and logic unit (ALU) is one of the main bases to define the system performance. Its plan depends on combinational circuits that decrease complexity and it has reasonable simulation times. Cell misalignment, cell displacement, cell omission (missing cell), and the extra (additional) cell are considered as the weaknesses of these circuits. Designing Fault tolerance of ALU in QCA is very important but there is no survey about the details. A three-level fault-tolerant ALU based on QCA is discussed in this paper, which performs “AND”, “OR”, “XOR” and “Full adder”. Also, the used rotated majority gate in the proposed ALU is fault tolerance. This structure tolerances a single stuck-at 0 and 1 and related faults are covered using test patterns {11100, 11101, 11010, 11001}. Furthermore, the presented ALU, under omission errors of cells in layers 2 and 3 is tolerated using the test patterns. The presented method has high fault tolerance compared to the similar methods according to the simulation results using QCAdesigner. It also has 0.78 µm2 of circuit area and the outputs are delivered after three clock cycles. Also, it has lower area consumption and delay compared to other schemes.