A new technique for exploiting regularity in data path synthesis

Abstract

Exploiting Regularity has been the key to the success of many techniques for digital systems design. This paper presents a novel approach for exploiting the regularity in memory access that exists in many DSP and matrix computations, in order to reduce the access delay of memory and to cut down hardware cost. In this approach, data (variables) that have regular access patterns are not stored in a random access memory element; instead they are kept floating in special storage structures called sequencers, thus avoiding the bottleneck of accessing random access memories and register files and saving the overhead of memory address generation and decoding. A theoretical foundation for modeling the allocation of two types of sequencers, namely queues and stacks, is established. In addition, algorithms are developed to map variables to queues and stacks and to integrate them into conventional high-level synthesis procedures. Experimental results show an encouraging improvement in the performance of designs as well as a significant reduction in hardware cost.