Abstract
A small-area static memory cell with high soft-error immunity is proposed. The driver MOSFET has a vertical structure. Its source region is buried in the substrate to which the ground potential is applied on order to shield the surface drain region from noise charges. The transfer MOSFET is a lateral type. These changes result in a reduction of the memory cell size and the gate area with the same effective gate width, since the channel is formed around the trench gate electrode. High soft error immunity is also expected because the drain region is shielded from noise charges induced by a-particles. A test circuit for a 1-bit memory cell was fabricated by using the 1.3 mu m process technology. The cell size was 0.75 times as large as the conventional memory cell size, and its soft error rate was only 0.04 times that of the conventional one. The results show that this memory cell is suitable for future multimegabit SRAMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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