A New Salicidation Process with Solid Antimony (Sb) Segregation (SSbS) for Achieving Sub-0.1 eV Effective Schottky Barrier Height and Parasitic Series Resistance Reduction in N-Channel Transistors

Abstract

We report a new CMOS-compatible salicidation process to achieve sub-0.1 eV effective Schottky barrier (SB) height for NiSi/n-Si, one of the lowest values reported-to-date, and its device integration for contact resistance reduction in n-FETs. A thin solid Antimony (Sb) layer is inserted beneath Ni prior to S/D silicidation, acting as a large source of n-type dopants. After silicidation, a very high concentration of Sb is incorporated at the NiSi/Si interface. This solid Sb segregation (SSbS) process reduces the effective SB height and parasitic series resistance. The SSbS process leads to enhanced n-FET performance without degradation in off-state leakage.