Abstract
With the effects of equivalent oxide charges on the flat-band voltage, a new quasi-three-dimensional (quasi-3-D) compact threshold voltage model is presented for the pi-gate (ΠG) MOSFETs with the interface trapped charges based on the quasi-3-D scaling equation that accounts for equivalent number of gates and virtual back gate effects induced by the normalized gate extension depth in the buried oxide. The model reveals that a thin gate oxide can effectively reduce the threshold voltage degradation caused by the trapped charges. Opposite to the thin gate oxide, a thick silicon is required to alleviate the threshold voltage shift resulted from the negative trapped charges. For the short-channel behavior, the device with negative/positive trapped charges can decrease/increase the threshold voltage roll-off caused by the short-channel effects. Due to its computational efficiency and simple formula, the model can be easily used to explore the threshold behavior for the charges trapping ΠG MOSFETs.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
