A new power estimation technique with application to decomposition of Boolean functions for low power

Abstract

Logic level circuit optimization for low power requires e cient estimation of the number of transitions occuring on signals internal to a circuit. We introduce a new technique based on Markov chains to estimate the transition probabilities of internal signals. Both temporal dependence and multiple concurrent transitions of primary inputs are taken into account. Functional decomposition of Boolean functions is an important synthesis step, especially for look-up-table FPGAs. Typically, functional decomposition optimizes circuits for low area. In this paper we introduce modi cations to this method to nd solutions with low power consumption. The modi ed functional decomposition is controlled by the estimated transition probabilities. Detailed experiments on benchmarks demonstrate a reduction of power consumption by 27% on average at a small cost of 5% area increase.