A new power efficient current-mode 4-PAM transmitter interface for off-chip interconnect

Abstract

In this work we propose a power-efficient 4-PAM current-mode transmitter for high-speed chip-to-chip data communication applications. The proposed transmitter meets the impedance requirements of current-mode communication. It offers high output impedance for outbound signal, a requirement of a current-mode transmitter and simultaneously provides back impedance of 100-Ω differential for reflections coming from the line. This unique feature offers significant power savings compared to a conventional 4-PAM transmitter for target signal swing. The proposed back terminated transmitter is implemented in 1.8-V, 0.18-μm digital CMOS technology, which takes into device parasitic and second order effects. The 4-PAM transmitter able to support data rates of 10-Gb/s over a FR4 PCB trace of length 7.5-inch for a target bit-error rate(BER) of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . The industry standard 7.5-inch FR4 PCB trace is modeled by measured 4-port S-parameters in the frequency range from 100-MHz to 20-GHz. The power consumed in the 4-PAM transmitter is 10.2-mW, this power is 37.5% lower than a conventional passive terminated current-mode 4-PAM transmitter power consumption.