Abstract
This paper introduces a new technique that uses a differential amplifier in closed-loop negative feedback configuration to measure the offset of a dynamic latch. This offset can then be stored and canceled using standard techniques, thus allowing gain reduction in the preamplifier stages in high-resolution comparators. A CMOS comparator was designed based on the proposed technique. The output of the comparator drives a 1 pF load capacitance and is held valid for at least 75% of the cycle. The performance of the comparator was simulated using HSPICE with the worst-case combination of differences as large as 10 mV between the thresholds of nominally identical transistors, where it achieved an offset of 400 /spl mu/V at a 40 MHz clock rate in 0.6 /spl mu/m CMOS technology while dissipating 1 mW from a 3.3 V power supply.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
