A new modified I-MOS varactor for linear range enhancement

Abstract

High linear MOS varactors can reduce AM to PM conversion and phase noise of the LC-VCOs. In this paper, a new technique is presented to increase the linear range of MOS varactors by reducing the slope of the C–V characteristic in linear region. In the proposed method, instead of using only one MOS varactor with aspect ratio of W/L, several varactors (e.g. n = 2, 3, …) with (W/n)/L are connected in parallel. The substrate of each varactor is biased at different voltage to shift its C–V linear region by changing the threshold voltage. In this way, each sub-varactor in the proposed structure covers different linear region of the whole varactor. Hence, the overall linear range of the parallel varactors can be significantly increased by correctly biasing of the substrates. To verify the proposed method, a MOS varactor including 6 parallel sub-varactors is designed in a commercial TSMC 0.18 μm CMOS Technology. Simulation results show 4× improvement of the linear range than conventional varactors and nearly constant VCO gain in tuning range. Furthermore, using the proposed varactor in a conventional LC oscillator, 10 dB improvement of the phase noise is achieved.