A new memory-reduced architecture design for log-MAP algorithm in turbo decoding

Abstract

In coding theory, turbo codes have been the breakthrough in recent years. Among these, the MAP (maximum a posteriori) algorithm is a powerful SISO (soft-input soft-output) algorithm for turbo decoding. However, MAP decoders of the turbo decoding consume large memories in hardware implementation. This work presents a new architecture for memory reduction in log-MAP (logarithm-MAP) algorithm. Based on the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. In addition, we also simplify the memory data access without extra address generators.