A New Memory Consistency Model for Real-Time Multicore Processors

Abstract

Several relaxed memory consistency models have been proposed to improve performance with reduced messages and data on software/hardware distributed shared memory. This paper proposes a new relaxed consistency model, Midway between Eager and Lazy release consistency (MEL), for real-time RISC-V multicore embedded processors. MEL ensures that memory accesses inside critical sections obtain the latest values with reduced communication latency by using ff_load and fu_store instructions [1]. We evaluate MEL with test programs in terms of necessary hardware resources.