A New Low-Costing QC-LDPC Decoder for FPGA

Abstract

Based on the Generalized Distributive Law and the features of FPGAs, this paper proposes a new strategy for implementation of Low-Costing QC-LDPC Decoder on FPGA platform. We get this new strategy from the Generalized Distributive Law, which is proposed to describe the belief propagation on graphs. And using this new strategy a low-costing (2560, 1024) LDPC decoder is implemented on a Xilinx Virtex-4 FPGA. Results show that this new strategy can make good use of the performance of LDPC codes, even though it needs less resource.