A New Interface Technique for the Acquisition of Multiple Multi-Channel High Speed ADCs

Abstract

Multi-channel high speed ADCs with a serial output interface operating at several hundred Mbps have been introduced several years ago. Interfacing to these high speed devices poses new challenges to the designer. Existing techniques usually rely on delay locked loops, require several milliseconds to reach stable operation, and do not guarantee a fixed latency making the accurate synchronization of several multi-channel ADCs difficult to achieve. A new interface technique is introduced to overcome these limitations. We detail the proposed method and show an implementation where a single field programmable gate array is used to collect data from twenty four 12-bit ADC channels clocked at 20 MHz.