A New Gate Dielectric for Highly Stable Amorphous-Silicon Thin-Film Transistors With $\sim\!\! \hbox{1.5-cm}^{2}/\hbox{V} \cdot \hbox{s}$ Electron Field-Effect Mobility

Abstract

Hydrogenated amorphous-silicon (a-Si:H) thin-film transistors (TFTs) in the bottom-gate back-channel-cut geometry were made with a homogeneous SiO2-silicone hybrid as the gate dielectric. The dielectric is deposited in a plasma-enhanced chemical vapor deposition (PE-CVD) system at nominal room temperature, and the a-Si:H channel and n+ source/drain layers are deposited by PE-CVD at 150degC. The threshold voltage VT is ~3V, the subthreshold slope is S ~ 290 mV/decade, the electron field-effect mobility is mu~1.5 cm2/Vldrs, and the on/off current ratio is ~107. The threshold-voltage shift DeltaVT under high-field gate bias is approximately one-half of that in conventional a-Si:H/SiNx TFTs fabricated at 300degC . These results suggest that the SiO2-silicone hybrid material may become the gate dielectric of choice for a-Si:H TFT applications that require high transconductance and high stability.