A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture

Abstract

A conventional duo binary transmitter needs a clock frequency equal to transmission data rate and for high speed data transmission the clock frequency defines the transmission limit. In this work we propose a double data rate duo binary transmitter architecture. It uses a clock frequency half of the output data transmission rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duo binary transmitter. In this architecture, duo binary precoder is integrated into the last stage of a tree structured serializer to combine two high speed NRZ data streams at half the output data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper back plane where the channel transfer characteristic is exploited to provide the duo binary spectral shaping and the transmitter performs duo binary precoding. In the second mode, filtering operation follows duo binary precoding at the transmitter and hence is applicable for optical transmission where the high bandwidth channel can not provide the required spectral shaping. A delay locked loop(DLL) based clock multiply unit(CMU) is employed to generate a high frequency, low jitter clock with 50% duty cycle needed for the realization of the proposed transmitter architecture. The design is implemented in 1.8-V, 0.18-?m Digital CMOS technology. The duo binary transmitter circuit works up-to 10-Gb/s speed and consumes 20-mW power.