A new digital control system for CESR-C and the cornell ERL

Abstract

Recent progress in developing digital low-level RF controls for accelerators has made digital systems an option of choice. At Cornell we are presently working on two projects: upgrading the RF controls of the Cornell Electron Storage Ring (CESR) for charm-tau operation (CESR-c) and developing a new low-level RF system for the proposed Cornell energy-recovery linac (ERL). The present CESR RF control design is based on classic analog amplitude and phase feedback loops. In order to address the required flexibility of the RF control system in the CESR-c upgrade and to implement a true vector sum control we have designed and built a new digital control system. The main features of the new controller are high sampling rates, high computation power and very low latency. The digital control hardware consists out of a powerful VME processing board with a Xilinx FPGA, an Analog Devices digital signal processor (DSP) and memory. A daughter board is equipped with four fast analog-todigital converters (up to 65 MHz sampling rate) and two digitaltoanalog converters (up to 50 MHz update rate). The first set of new electronics will be used in the CESR RF system. However, the described digital control hardware can also be used for the Cornell ERL as it was designed to meet its challenging field stability requirements (see [1] ).