A New Design Paradigm for Auto-Nonvolatile Ternary SRAMs Using Ferroelectric CNTFETs: From Device to Array Architecture

Abstract

Preserving the data stored in a static random access memory (SRAM) during power gating or a sudden power outage is a necessary but costly need. This work proposes an ultraefficient auto-nonvolatile ternary SRAM (ATSRAM) cell using ferroelectric carbon nanotube field-effect transistors (Fe-CNTFETs). By harnessing the unique features in Fe-CNTFETs, the proposed ATSRAM utilizes only 12 transistors. The proposed design can automatically perform backup and restore operations without additional resources and nonvolatile elements during a power outage. This unique specification eliminates the redundancies usually required to provide nonvolatility. The utilized hysteretic cross-coupled two-transistor standard ternary inverters (STIs) provide a superior static noise margin (SNM) beyond the binary SRAMs and the ideal noise margin limitation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}}$ </tex-math></inline-formula> /4). The proposed ATSRAM array structure benefits from a row-shared supply disconnector to mitigate the static current drawn from the power supply during data retention. Our results demonstrate that the proposed ATSRAM indicates, on average, 40% improvement in transistor count, 2.8 times higher SNMs, 27% reduction in total power consumption, and 41% (66%) improvement in the read (write) energy compared with the state-of-the-art volatile ternary SRAMs. In a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${32} \times {32}$ </tex-math></inline-formula> ternary array configuration, 94% (98%) improvement in the read (write) energy is obtained compared with the other counterparts. Our design methodology provides a new paradigm for designing ultraefficient and ultracompact nonvolatile multivalued logic (MVL) memories using ferroelectric-based FETs.