A new design of digitally controlled oscillator for low power applications

Abstract

With the utilization of all-digital Phase locked loops (ADPLLs) in digital communication systems, the use of digitally controlled oscillators (DCO) over voltage controlled oscillators (VCO) has come into existence. In this paper, a new low power DCO structure is proposed with NMOS transistor as switching network. The DCO design is based on the CMOS inverter delay cells and ring topology. Three and five stages DCO architecture with three and four control bits have been designed here with a NMOS switching network. Three-bit DCO with three delay stages shows a variation of output frequency and power consumption in the range of 1.804–2.629 GHz and 44.464–73.023 μW, respectively. For three-bit five-stages DCO the output frequency and power consumption varies in the range of 1.004–1.479 GHz and 74.107–121.705 μW. A four-bit, three-stages DCO shows a variation of output frequency and power consumption in the range of 1.948–2.875 GHz and 44.464–85.489 μW. Similarly, a four-bit five-stages DCO provides a variation of output frequency and power consumption in the range of 1.115–1.676 GHz and 74.107–142.482 μW. The control bits for the three-bit DCO are varied from [001] to [111] and for four-bit DCO the control bits are varied from [0001] to [1111]. The simulations are done using Mentor Graphics tool with TSMC 0.18 μm CMOS technology.