A new design leads to efficient bit-serial FPGA implementation for the biorthogonal 5/3 DWT filter bank

Abstract

In this paper, an efficient design of the lattice structure of the biorthogonal 5/3 discrete wavelet filter bank is introduced and then implemented using the technique of bit–serial implementation. This technique is usually used when area has a significant importance for the designer, where it is possible to be used for the designs that consist of similar parts of processing elements. Using VHDL language, the FPGA Spartan–3E device is exploited for implementing the designed structure. The implementation complexity (utilised chip area) of the resulting structures is significantly reduced as compared with the pipelined implementation of the same design. It also outperforms another efficient implementation of the same filter bank using lifting scheme.