Abstract
We propose a new scheme for the Texas Instruments SN54182/SN74182 lookahead-carry generator. The SN54182/SN74182 provides a redundant carry output, C/sub n+x/. Our re-design provides an alternative to the original design that improves the performance of adder implementations. We analyze gate delays of lookahead adders with sizes of 16, 32 and 64 bits. The examine both CMOS-AISC vendor technology and standard TTL implementations, in all cases, gate delays of sum and carry bits are improved. >
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