Abstract
Comparators are the main components in several analog and mixed-signal systems. Design and synthesis of comparator architectures largely remain an analog designer’s art. In this work, we present a systematic methodology for designing comparators using the method of constrained optimization. Constrained optimization is an equation-based optimization method and requires accurate equations. We propose a new delay equation for latch-based comparators. The new delay model is based on Adomian decomposition method and gives more accurate delay characteristics compared with the conventional one. The architecture is optimized for total power dissipation with speed, area and noise as the constraints. Geometric programming-based automation algorithm and the behavioral model of the comparator architecture are written in MATLAB. The optimized schematic is drawn in Cadence 180 nm technology, and the results are verified with MATLAB.
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