Abstract

A wideband radio-frequency (RF) receiver front-end is designed in 0.18 /spl mu/m CMOS technology with a new linearization technique that makes the circuit suitable for operating at low supply voltage. The proposed front-end circuit includes an input low noise wideband amplifying stage (LNA) of new configuration with output linearized transconductance stage, and a switching stage. Dual-loop resistive feedback applied around the LNA allows one to achieve input wideband matching. Linearity is enhanced by attenuating the effective transconductance of the transconductance stage. With an RF input signal of 1.9 GHz, the proposed front-end circuit exhibits 15.5 dB conversion gain, 7.2 dB SSB noise figure, -11.2 dBm 1-dB compression point, and -1.5 dBm third-order input intercept-point (IIP3) in simulations. The input wideband matching to 50 /spl Omega/ is achieved with -3 dB bandwidth of around 3 GHz. The input return loss (S11) varies from -26 dB to -10.5 dB in the frequency range of DC to 3.5 GHz. The proposed front-end consumes 22.3 mA DC current from 1.8 V supply voltage and occupies an area of 0.9/spl times/0.85 mm/sup 2/.

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