A new CMOS programmable gain controller with a wide dynamic range

Abstract

In this paper, a new structure is proposed to implement a programmable gain controller with a wide dynamic range. The timing-duty controlled structure determines the attenuation values by changing the ratio of the integration time between the desired attenuation value and unity gain instead of the resistor or capacitor ratios. It reduces the chip area by applying the timing-duty controlled concept on switched capacitor (SC) circuits. But in the original timing-duty controlled circuit the system clock frequency would be too high to be implemented in order to have a high resolution. A new timing-duty controlled programmable gain controller (TDGC) is proposed and reduces the required system clock frequency by one-third and one-fourth successfully. There are two advantages of this new structure: one is the absence of the selectable capacitor array - thus it takes up less chip area than ordinary SC circuits. The other is that the TDGC circuit is used more efficiently by modifying the timing diagram and is feasible to be applied to the SC circuits. The proposed programmable gain controller (PGC) circuit has 80 level settings of the LOSS range from 0 dB to -79 dB by a step of -1 dB. It has monotonically logarithmic increments with maximum deviation of -0.53 dB in the range of 0 dB to -59 dB and -0.83 dB in the range of 0 dB to -79 dB.