A New CMOS four-quadrant analog multiplier with differential output

Abstract

This paper presents a new four-quadrant analog multiplier circuit based on a new symmetrical configuration designed in CMOS technology. The proposed circuit is suitable for low voltage and low power applications. Compared to the corresponding already published works, the dynamic input and output ranges of the circuit are improved owing to the fact that the circuit works in the saturation region not in weak inversion. High accuracy is the further advantage of the circuit. In order to simulate the circuit, HSPICE simulator is utilized to verify the validity of the theoretical analysis in 0.18 µm CMOS technology, where under supply voltage of 1.5 V, the input range of the proposed circuit is ±400 mV, total power consumption is 44 µW, and the corresponding nonlinearity remains as low as 1.5 %. Moreover, the band-width of the circuit is found to be 196 MHz.