Abstract
The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically about 30% to 70% of the total dynamic (switching) power consumption. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. In this work, a new methodology is applied for gating the Flip flop by which the power will be reduced. The clock gating is employed to the pipelining stage flip flop which is active only during valid data are arrived. The methodology used in project named Selective Look-Ahead Clock Gating computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. Similarly to data-driven gating, it is capable of stopping the majority of redundant clock pulses. In this work, the circuit implementation of the various blocks of data driven clock gating is done and the results are observed. The proposed work is used for pipelining stage in microprocessor and DSP architectures. The proposed method is simulated using the quartus for cyclone 3 kit.
Highlights
In digital systems, power consumption becomes a most important parameter to be reduced
Serious timing constraints are imposed on those FFs residing on critical paths, which avoid their gating. These drawbacks are rectified in look-ahead clock gating (LACG) which works on gating the master latch making it applicable for large and general designs and avoiding the tight timing constraints
The 3 stage pipeline architecture consists of 3 M-Bit flip-flops and gates as combinational block
Summary
Power consumption becomes a most important parameter to be reduced. Clock gating is one of the design methodologies for reducing the power consumed by digital systems. Serious timing constraints are imposed on those FFs residing on critical paths, which avoid their gating These drawbacks are rectified in look-ahead clock gating (LACG) which works on gating the master latch making it applicable for large and general designs and avoiding the tight timing constraints. It is subsequently shown that clk_g probability is very low and it is not further being gated An overhead in this design is the consumption of power in the additional FF used for gating
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