Abstract
This paper proposes a new pipelined analog to digital converter (ADC) based on second-generation current conveyors (CCII). Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifiers (OA). Simulation results show that the proposed CCII-based pipelined ADC can work at 10 MHz with an 8-bit resolution. The DNL is within -0.4 LSB and 0.5 LSB and INL is within -0.4 LSB and 0.7 LSB, respectively. The ADC is realized in TSMC 0.35 /spl mu/m CMOS technology and consumed 29 mW under a 3.3 V power supply. The core size is 0.85/spl times/0.85 mm/sup 2/.
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