A New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256)

Abstract

Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures are mandatory. State-of-the-art decoding algorithms result in architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall complexity. To the best of our knowledge, we propose the first architecture for high speed, low latency Non-Binary Low-Density Parity-Check Check Node processing for GF(256). It has state-of-the-art communications performance while largely reducing the hardware complexity. The presented architecture has a 3.3 times higher area efficiency, increases the energy efficiency by factor 2.5 and reduces the latency by factor of 5.5 compared to the first implementation of Check Node for GF(256) based on the state-of-the-art FWBW scheme that was also implemented in the scope of this work.