Abstract
Recent improvements in fabrication technology have made possible the realization of reliable integrated circuits (ICs) containing both analog and digital functions on the same silicon chip. Hence analog blocks, like filters, ampli- fiers, ADCs etc. are present before digital blocks in mixed signal VLSI circuits. This imposes restrictions on access- ing directly the pins of digital blocks resulting in drop of fault coverage. So DFT techniques like boundary scan are employed to solve this problem. In this paper we propose a new methodology for testing digital blocks embedded in mixed signal VLSI circuits that reduces the DFT overhead. In this methodology we develop an algorithm based on ana- log back trace for generating and applying test patterns to these digital blocks using the on-chip analog circuitry. The scheme is shown to work reasonably even with parameter variations of the analog blocks. Keywords: Automatic Test Pattern Generation, Analog back trace, Sensitivity analysis, Behavioral model
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.