Abstract
This paper proposes and develops an original power-efficient reversed nested Miller compensation technique for low-power three-stage amplifiers driving large capacitive loads. The proposed approach exploits dual-active buffers in the compensation network, along with a feedforward gain stage providing enhanced speed performance. A well-defined design procedure for the compensation elements is also developed using the loop-gain phase margin as the main design parameter. To confirm the effectiveness of the proposed technique, SPECTRE simulations on a three-stage amplifier driving a 1-nF capacitive load are carried out adopting the model parameters of a standard 0.35 mum CMOS technology. Simulation results are finally found to be in excellent agreement with the theoretical analysis, showing a considerable improvement of the proposed strategy over other traditional solutions in terms of small-signal and large-signal performance.
Published Version
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