A New Accurate and Efficient Timing Simulator

Abstract

Timing simulation has always been considered a crucial step in digital VLSI circuit designs. Many researchers have addressed the issues of time eficiency us. accuracy by using simpler device models and by simplifying the numerical algorithms. In this paper, a Stepwise Equivalent Conductance circuit simulation technique is presented, which treats every nonlinear device as a linear time-varying conductor. No Newton Raphson iteration is needed for the implicit integration. The convergence of the simulation is guaranteed. A timing simulator, SWEC, has been built based on the proposed technique. Moreover, the simulator exploits the piecewise linear voltage waveform property of digital MOS circuits to further speed up the simulation. SWEC can handle very large CMOS designs. The com arisons with Relax23 [5], SPLICE.9.0 [4], XPsim [21 and SPECS2 [.9] indicate that the simulator exhibits better efficiency and accuracy.