A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

Zulqar Nain,Rashid Ali,Muhammad Khalil Afzal,Sheraz Anjum,Sung Won Kim

doi:10.3390/electronics9071076

Zulqar Nain, Rashid Ali + Show 3 more

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https://doi.org/10.3390/electronics9071076

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Abstract

Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.

Highlights

The contracting size of transistors to submicron levels leads to a large number of cores combined onto a chip known as a system-on-a-chip (SoC)
network adaptive fault-tolerant routing (NAFTR) achieved a lower latency and higher throughput compared to efficient dynamic and adaptive routing (EDAR), as indicated by the results presented in the experimental results section
The proposed routing algorithm NAFTR was compared with EDAR and fault-tolerant XY (FTXY)

Summary

Introduction

The contracting size of transistors to submicron levels leads to a large number of cores combined onto a chip known as a system-on-a-chip (SoC). The bus-based architectures of SoCs are not able to meet the growing diverse communication requirements. According to Moore’s law, the doubled packing density of micron technology is achievable every eighteen months. SoC architectures are unable to exploit the availability of these doubled PEs after every eighteen months due to latency and power nightmares [1]. Network-on-a-chip (NoC) architectures have evolved to overcome these growing challenges experienced by SoC architectures. An NoC’s communication is based on packet routing networks instead of the wires and busses used in SoC. NoC architectures are used to provide the advantages of Electronics 2020, 9, 1076; doi:10.3390/electronics9071076 www.mdpi.com/journal/electronics

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