Abstract
A negative word-line voltage negatively-incremental erase pulse scheme is proposed for the enterprise solid-state drive (SSD) application ferroelectric (Fe)-NAND flash memories. The negative word-line voltage erase accelerates the erase pulse ramp-up from 1 ms of the conventional well erase to 2 µs and a 200 µs/page erase is realized. The erase characteristics with various erase pulse shape such as the fixed erase pulse, the variable time erase pulse, and the proposed negatively-incremental erase pulse for the Fe-NAND cells are investigated. With the proposed scheme, the erase voltage, VERASE decreases by ΔVERASE. The measured VTH shift, ΔVTH, is constant at 1/6ΔVERASE, which is different from that of the floating-gate NAND cells where ΔVTH = ΔVERASE. The mechanism of the constant ΔVTH is discussed with the major and the minor polarization–electric field curves. By combining the proposed negatively-incremental erase scheme with the bit-by-bit verify, a narrow erase VTH distribution of 0.07 V is achieved with ΔVERASE of 0.4 V.
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