Abstract
A fully-parallel minimum Hamming-distance search memory has been designed, which uses digital circuitry for bit-comparison and fast analog circuitry for word-comparison as well as winner-take-all (WTA) functionality. The approach allows compact and high-performance integration in conventional CMOS technology. The 0.6 /spl mu/m, 2-poly, 3-metal CMOS design with 32 rows and 128 columns achieves <100 ns search times at <260 mW power dissipation. The approach is extendable to increased pattern length and larger row numbers and enables high efficiency for pattern-matching applications such as network routers, code-book-based data compression, or object recognition. As for conventional memories, high yield can be achieved with a redundancy concept for rows (including WTA function) and columns.
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