A Near-Accurate-Parasitic-Balancing Sensing Scheme for PCM With 8.9-ns Read Access Time and 16.2-ns·pJ/Kb FoM

Abstract

Phase change memory (PCM) is promising to fill the large latency and density gap between storage and memory. The long bit line (BL) design increases the density but results in a long read access time, which has been a typical design challenge. This letter proposes a near-accurate-parasitic-balancing sensing scheme to improve the chip speed. The sense amplifier utilizes a low power balancing circuit and a parasitic balancing circuit. A dummy read transmission gate and n-1 OFF PCM cells are introduced in the read reference circuit. The proposed scheme achieves a more accurate balance of read and reference parasitics with fewer reference resistances and capacitors used, compared to the conventional one. A 256-Kb 1024-BL-length PCM is fabricated in a 130-nm CMOS technology and demonstrates an 8.9-ns read access time and a 16.2-ns·pJ/Kb Figure-of-Merit (FoM) at 25 °C. The FoM is suppressed by over 2.5×, compared to the state-of-the-art fabricated PCM.