A Multiplying Delay-Locked Loop design with low jitter and high linearity

Abstract

In this paper, a Multiplying Delay-Locked Loop (MDLL) for high-precision Time to Digital Converter(TDC) is proposed, which has low jitter and high delay linearity. In order to reduce the phase noise, an internally compensated charge pump(CP) is used to achieve better current matching between charging and discharging. The improved reverse differential delay cell structure is used to improve the resolution of multi-phase clock. An MDLL with an output frequency of 80-240MHz and an area of 0.08mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is realized by using 0.18um CMOS process. The test results show that the total power consumption under 1.8V power supply is 11.52mW@240MHz, RMS jitter is 10ps@240MHz.