A Multiplier Structure Based on a Novel Real-time CSD Recoding

Abstract

Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multiplications. In this paper, we introduce a novel multiplier structure that converts from 2's complement to canonical signed digit (CSD) representation in real time. The proposed algorithm increases the number of zero partial products (which can be simplified by shift operations) to approximately 66.7% compared with 50% for modified Booth's recoding. Also, the proposed hardware structure reduces the non-zero partial products to a minimum, and consequently the number of arithmetic operations in the carry-save structure is reduced. So, our proposed hardware decreases both the time required for multiplication and the power consumption of the multiplier. Furthermore, because the proposed structure uses real time CSD recoding, and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be used to implement digital filters with non-fixed filter coefficients, such as adaptive filters.