Abstract
A 12-channel TDM/FDM translator consisting of six VLSI digital signal processors is described. A filter bank which consists of a discrete cosine transform and a polyphase network of 14 filters is realized by three processors and effects the translation each way. One processor provides synchronization between the 96 kHz TDM and 112 kHz FDM signals and performs the cosine transform, and the remaining two do the filtering. The polyphase procedure is reviewed, a simplified development of the fast discrete cosine transformation is presented, and a new structure for the filters is introduced. The main opportunities for computational reduction are seen to be in the filtering. An algorithm for the filters is presented which is optimal with respect to efficiency and roundoff noise for a processor with a single multiplier accumulator. The VLSI processors discussed are seen to be Very effective in this realization because of their efficiency in this type of filtering and because of their intercommunication and synchronization capabilities.
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