A multiple phase partial scan design method

Abstract

Partial scan design is divided into two stages: (1) critical cycle breaking, and (2) partial scan flip-flop selection with respect to conflict resolution. A multiple phase partial scan design method is introduced by combining circuit state information and conflict analysis. Critical cycles are broken using a combination of valid circuit state information and conflict analysis. It is quite cost-effective to obtain circuit state information via logic simulation, therefore, circuit state information is iteratively updated after a given number of partial scan flip-flops have been selected. Valid-state-based analysis may become ineffective to select scan flip-flops when cycles remaining in the circuit are not influential to testability. The method turns to the conflict resolution process using an intensive conflict-analysis-based testability measure of conflict. Sufficient experimental results are presented.