Abstract
More and more attention is being paid to the use of massive parallel computing performed on many-core Networks-on-Chip (NoC) in order to accelerate performance. Simultaneously deploying multiple applications on NoC is one feasible way to achieve this. In this paper, we propose a multi-phase-based multi-application mapping approach for NoC design. Our approach began with a rectangle analysis, which offered several potential regions for application. Then we mapped all tasks of the application into these potential regions using a genetic algorithm, and identified the one which exhibited the strongest performance. When the packeted regions for each application were identified, a B*Tree-based simulated annealing algorithm was used to generate the optimal placement for the multi-application mapping regions. The experiment results show that the proposed approach can achieve a considerable reduction in network power consumption (up to 23.45%) and latency (up to 24.42%) for a given set of applications.
Highlights
Approach for Many-CoreDue to the advancement of transistor technology, hundreds to thousands of processors or cores have been integrated on a single chip
Thea genetic algorithm (GA), which is similar to the single application mapping described in reference fitness of each chromosome is evaluated in the second step
Used to map all tasks of the individual application into these potential regions and identify the one based mapping algorithm was used to map all tasks of the individual application into which exhibited the regions strongestand performance
Summary
Due to the advancement of transistor technology, hundreds to thousands of processors or cores have been integrated on a single chip. A multi-objective adaptive immune algorithm which considered different various delay constraints for multi-application mapping was proposed in [12] In these studies, multiple applications reused the same platforms in different time slots. Yang et al [4] proposed a multi-application mapping method to identify an optimal mapping region for each application. It dealt with multiple applications sequentially on a fixed platform. The aim of our proposed approach is to identify the best performance for each individual application mapping, packet each application mapping region as a block to determine placements for all the applications with a minimized mapping area of the NoC platform.
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