Abstract
A multi-modulus programmable frequency divider architecture with 33.3% to 66.7% duty cycle output signal is presented. Key circuits of the architecture are 2/3 divider cells, which share the same logic and almost same circuit cells. This architecture can divide the input clock frequency by 22 to 2n+1 −1 with unit step increment, where n is the number of 2/3 divider cells; and 33.3% to 66.7% duty cycle output signal greatly improve output load driver capable.
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