A Multiloop Method for Minimization of Parasitic Inductance in GaN-Based High-Frequency DC–DC Converter

Abstract

Gallium nitride high electron mobility transistors (GaN HEMTs) are promising switching devices in high-efficiency and high-density dc–dc converters due to their fast switching speed and small conduction resistance. However, GaN HEMTs are very sensitive to parasitic inductance because of their high switching speed, low-threshold voltage, and small driving safety margin. Parasitic inductance can cause severe voltage overshoot and ringing, which may result in electromagnetic interference issues, false turn-on, or even device breakdown. This paper aims at reducing the parasitic inductance (including power loop inductance and driver loop inductance) by optimizing the layout. First, a multiloop method is proposed to reduce the parasitic inductance. Optimization of both the conventional single-loop structure and the proposed multiloop structure are presented. Second, three kinds of power loop layouts based on the proposed multiloop structure are realized on PCB substrate and one of them is realized on aluminum nitride (AlN) substrate, which has higher thermal conductivity but less copper layers. The power loop inductance on PCB substrate is reduced to 0.1 nH, which is only 25% of the state-of-art layout. The power loop inductance on AlN substrate is reduced to 0.22 nH. Third, the driver loop layout is optimized and achieves 50% reduction of driver loop inductance compared with the conventional single-layer layout. Finally, integrated modules using the proposed layouts are built to validate the analyses and designs.