A multi-level DRAM with fast read and low power consumption

Abstract

In this paper, we present a new, multi-level DRAM design, which can store 3 voltage levels (0, Vcc, and Vcc/2) in a single memory cell. This multi-level DRAM requires no special reference voltage and simplifies design of the peripheral circuits. Coding algorithms may be used to provide binary data immediately after first read, with the second read operation providing a second data word from the same cell; thus, binary data from two logical addresses can be obtained from one physical location. One of the coding algorithms uses an additional coding memory cell for every two data memory cells to provide 4-bits of binary data. A second algorithm uses 3 additional coding cells for every 8 data cells to provide 8-bit binary data for each access; thus every 11 memory cells can provide 16 bits of binary data. Furthermore, the read speed is faster than a conventional DRAM because the first access can complete before the word line reaches Vccp, and because a SRAM differential sense amplifier is used. Finally, storing 3 voltage levels in a single memory cell also reduces average power consumption, since the Vcc/2 voltage level requires less write back current than 0 or Vcc voltage level