Abstract
The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than ±0.9 LSB and integral-non-linearity (INL) of better than ±1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology.
Highlights
The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN
A per bin adjustment feature to calibrate out device mismatch introduced by the interpolator structure as well as by the distribution buffers themselves is implemented inside the distribution buffers
This will force steep signal edges to be propagated across the loop and decreases the influence of device mismatches converted into timing errors
Summary
The proposed architecture, as shown in figure 1, employs a multistage concept using a DLL in the 1st stage and a passive interpolation concept [2] in the 2nd stage. Depending on the detailed implementation of the channels, a counter synchronization mechanism, to avoid an invalid code to be latched by the time capturing registers (TCR), might be necessary. This issue is well known in literature [3] and will not be discussed any further in this contribution. The generated time code (interpolator + counter) is distributed to connect to the respective channels of the TDC, here referred to as the channel matrix. No local interpolation is required on a channel per channel basis avoiding the need to calibrate each channel separately
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